Method of manufacturing semiconductor device

ABSTRACT

A method of manufacturing a semiconductor device is provided. The method of manufacturing a semiconductor device includes forming a first electrode layer on a substrate, and then forming a stack structure on the first electrode layer, wherein the stack structure comprises a first insulating layer, a gate electrode layer, and a second insulating layer. An opening is formed in the stack structure. A gate dielectric layer is formed on a sidewall of the opening of the stack structure, and an oxide semiconductor layer is formed in the opening, wherein the gate dielectric layer is sandwiched between the oxide semiconductor layer and the gate electrode layer. A second electrode layer is then formed on the stack structure to be in direct contact with the oxide semiconductor layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional application of and claims the prioritybenefit of U.S. patent application Ser. No. 17/386,565, filed on Jul.28, 2021, now allowed. The entirety of the above-mentioned patentapplication is hereby incorporated by reference herein and made a partof this specification.

BACKGROUND Technical Field

The invention relates to a semiconductor manufacture technique, andparticularly relates to a semiconductor device and a method ofmanufacturing the same.

Description of Related Art

The semiconductor device such as transistor has been developed for along time. The transistor includes plane device and vertical device. Theplane device is, for example, a thin film transistor, wherein a sourceelectrode and a drain electrode are over a gate electrode, and thechannel length (Lg) is defined by the spacing between the sourceelectrode and the drain electrode. However, the channel length isdesired to be smaller with the miniaturization of the device size, andthus the Lg of the plane device can not meet the requirement due to theresolution limitation of photolithography.

The vertical device is, for example, a 3D transistor, wherein a verticalchannel formed on the substrate, a source electrode and a drainelectrode are disposed at two ends of the vertical channel, and the Lgof the vertical device is defined by the thickness of a gate electrode.Therefore, the Lg of vertical device can be made smaller. However, theprocess of the vertical device is more complicated than the planedevice, and it is difficult in the formation and the contact fordrain/source/body.

SUMMARY

The invention provides a method of manufacturing a semiconductor deviceto obtain the semiconductor device having fine channel length.

The method of manufacturing a semiconductor device of one embodiment ofthe invention includes forming a first electrode layer on a substrate,and then forming a stack structure on the first electrode layer, whereinthe stack structure comprises a first insulating layer, a gate electrodelayer, and a second insulating layer. An opening is formed in the stackstructure. A gate dielectric layer is formed on a sidewall of theopening of the stack structure, and an oxide semiconductor layer isformed in the opening, wherein the gate dielectric layer is sandwichedbetween the oxide semiconductor layer and the gate electrode layer. Asecond electrode layer is then formed on the stack structure to be indirect contact with the oxide semiconductor layer.

In one embodiment of the invention, after the step of forming the secondelectrode layer, the method further comprises patterning the secondinsulating layer and the gate electrode layer.

In one embodiment of the invention, after the step of forming the secondelectrode layer, the method further comprises respectively formingelectrode contacts connecting to the first electrode layer, the gateelectrode layer, and the second electrode layer.

In one embodiment of the invention, the step of forming the gatedielectric layer comprises conformally depositing a dielectric materiallayer on the stack structure and in the opening, and then etching backthe dielectric material layer until the first electrode layer isexposed.

In one embodiment of the invention, the step of forming the stackstructure comprises depositing the first insulating layer on the firstelectrode layer, depositing the gate electrode layer on the firstinsulating layer, and depositing the second insulating layer on the gateelectrode layer.

In one embodiment of the invention, the step of forming the oxidesemiconductor layer in the opening comprises blanket depositing an oxidesemiconductor material to fill the opening, and then etching back theoxide semiconductor material until the stack structure is exposed.

In one embodiment of the invention, a method of forming the oxidesemiconductor layer in the opening comprises a selective depositionprocess.

In one embodiment of the invention, a material of the oxidesemiconductor layer comprises indium-gallium-zinc oxide.

In one embodiment of the invention, the substrate comprises asilicon-on-insulator (SOI) substrate.

Based on the above, since the invention provides a semiconductor devicehaving a planar stack structure containing two source/drain electrodes,a gate electrode layer therebetween, and an oxide semiconductorpenetrating through the gate electrode layer, it can realize finechannel length in the semiconductor device by simple process.

To make the aforementioned more comprehensible, several embodimentsaccompanied with drawings are described in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the disclosure, and are incorporated in and constitutea part of this specification. The drawings illustrate exemplaryembodiments of the disclosure and, together with the description, serveto explain the principles of the disclosure.

FIG. 1 is a schematic plan view of a semiconductor device according to afirst embodiment of the invention.

FIG. 2 is a cross-sectional view along line II-IF of FIG. 1 .

FIG. 3 is a schematic plan view of a semiconductor device according to asecond embodiment of the invention.

FIG. 4 is a cross-sectional view along line IV-IV′ of FIG. 3 .

FIG. 5A to FIG. 5I are schematic cross-sectional views of amanufacturing process of a semiconductor device according to a thirdembodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

Referring to the embodiments below and the accompanied drawings for asufficient understanding of the invention. These embodiments aredescribed in sufficient detail to enable those skilled in the art topractice the invention. However, the invention may be implemented inmany other different forms and should not be limited to the embodimentsdescribed hereinafter. Other embodiments may be utilized and structural,logical, and electrical changes may be made without departing from thescope of the present invention. In the drawings, for clarity, theelements and relative dimensions thereof may not be scaled. For easyunderstanding, the same elements in the following embodiments will bedenoted by the same reference numerals.

FIG. 1 is a schematic plan view of a semiconductor device according to afirst embodiment of the invention. FIG. 2 is a cross-sectional viewalong line II-IF of FIG. 1 .

Referring to FIG. 1 and FIG. 2 , the semiconductor device of the firstembodiment includes a substrate 100, a first electrode layer 102, a gateelectrode layer 104, a second electrode layer 106, an oxidesemiconductor layer 108, a gate dielectric layer 110, a first insulatinglayer 112, and a second insulating layer 114. The first electrode layer102 is disposed on the substrate 100, the gate electrode layer 104 isdisposed on the first electrode layer 102, and the second electrodelayer 106 is disposed on the gate electrode layer 104. In oneembodiment, the substrate 100 may be a silicon-on-insulator (SOI)substrate or other semiconductor substrate. The gate electrode layer 104may be made of conductive material such as indium oxide-tin oxide,indium oxide containing tungsten oxide, indium zinc oxide containingtungsten oxide, indium oxide containing titanium oxide, indium tin oxidecontaining titanium oxide, indium oxide, zinc oxide, or other suitablematerial. The first electrode layer 102 and the second electrode layer106 are as a drain and a source of the semiconductor device. Forexample, the first electrode layer 102 is a drain electrode and thesecond electrode layer 106 is a source electrode; alternatively, thefirst electrode layer 102 is a source electrode and the second electrodelayer 106 is a drain electrode. In one embodiment, the first electrodelayer 102 and the second electrode layer 106 may be a metal film or ametal nitride film, wherein the material of the metal film is selectedfrom Al, Cr, Cu, Ta, Ti, Mo, and W; the material of the metal nitridefilm is nitride of foregoing metal such as a titanium nitride film, amolybdenum nitride film, a tungsten nitride film), or the like. Theoxide semiconductor layer 108 penetrates through the gate electrodelayer 104 and is in direct contact with the first electrode layer 102and the second electrode layer 106, respectively. A material of theoxide semiconductor layer 108 includes, for example, indium-gallium-zincoxide (IGZO) or other suitable oxide semiconductor material. The gatedielectric layer 110 is disposed between the gate electrode layer 104and the oxide semiconductor layer 108, the first insulating layer 112 isdisposed between the gate electrode layer 104 and the first electrodelayer 102, and the second insulating layer 114 is disposed between thegate electrode layer 104 and the second electrode layer 106.

In the first embodiment, the profile of the cross section of thesemiconductor device is step-shaped, and thus it is beneficial tointerconnection of the semiconductor device. For example, an electrodecontact 116 connects to the first electrode layer 102, an electrodecontact 118 connects to the gate electrode layer 104, and an electrodecontact 120 connects to the second electrode layer 106. Those electrodecontacts 116, 118 and 120 can be formed together using the same steps.However, the invention is not limited thereto.

FIG. 3 is a schematic plan view of a semiconductor device according to asecond embodiment of the invention, wherein the reference symbols usedin the first embodiment are used to equally represent the same orsimilar components. FIG. 4 is a cross-sectional view along line IV-IV′of FIG. 3 . The description of the same components can be derived fromthe first embodiment, and will not be repeated here.

Referring to FIG. 3 and FIG. 4 , the semiconductor device of the secondembodiment also includes a substrate 100, a first electrode layer 102, agate electrode layer 104, a second electrode layer 106, an oxidesemiconductor layer 108, a gate dielectric layer 110, a first insulatinglayer 112, and a second insulating layer 114. The difference between thesecond and the first embodiments is that the shapes of the oxidesemiconductor layer 108 and the second electrode layer 106 are circular.In another embodiment, the shapes of the oxide semiconductor layer 108and the second electrode layer 106 in the FIG. 3 may be rectangle, andso on.

FIG. 5A to FIG. 5I are schematic cross-sectional views of amanufacturing process of a semiconductor device according to a thirdembodiment of the invention.

Referring to FIG. 5A, a first electrode layer 502 is formed on asubstrate 500. The substrate 500 may be a SOI substrate or othersemiconductor substrate.

Then, referring to FIG. 5B, a stack structure 504 is formed on the firstelectrode layer 502, wherein the stack structure 504, for example,includes a first insulating layer 506, a gate electrode layer 508, and asecond insulating layer 510. In the embodiment, the step of forming thestack structure 504, for example, includes depositing the firstinsulating layer 506 on the first electrode layer 502, depositing thegate electrode layer 508 on the first insulating layer 506, anddepositing the second insulating layer 510 on the gate electrode layer508.

Thereafter, referring to FIG. 5C, an opening 512 is formed in the stackstructure 504. The opening 512 may be, for example, a rectangle grooveor a circular hole. To form a gate dielectric layer on a sidewall 512 aof the opening 512, it may conformally depositing a dielectric materiallayer 514 on the stack structure 504 and in the opening 512 first.

After that, referring to FIG. 5D, the dielectric material layer 514 inFIG. 5C is etched back until the first electrode layer 502 is exposed soas to form the gate dielectric layer 514 a. However, the invention isnot limited thereto.

Then, referring to FIG. 5E, an oxide semiconductor layer 516 is formedin the opening 512, wherein the gate dielectric layer 514 a issandwiched between the oxide semiconductor layer 516 and the gateelectrode layer 508. In one embodiment, the step of forming the oxidesemiconductor layer 516 in the opening 512 includes blanket depositingan oxide semiconductor material (not shown) to fill the opening 516, andthen etching back the oxide semiconductor material until the stackstructure 504 is exposed. In another embodiment, a method of forming theoxide semiconductor layer 516 in the opening 512 includes a selectivedeposition process. A material of the oxide semiconductor layer 516includes, for example, IGZO or other suitable oxide semiconductormaterial.

Thereafter, referring to FIG. 5F, a second electrode layer 518 is formedon the stack structure 504 to be in direct contact with the oxidesemiconductor layer 516, wherein the method of forming the secondelectrode layer 518, for example, includes a deposition process. Asemiconductor device of the third embodiment has been manufactured inthis step.

After the step shown in FIG. 5F, there are some optional steps asfollows.

Please referring to FIG. 5G, the second electrode layer 518 is patternedto expose a portion of the stack structure 504.

Then, referring to FIG. 5H, the second insulating layer 510 and the gateelectrode layer 508 are patterned, and thus the profile of the crosssection of the structure in FIG. 5H is step-shaped for theinterconnection. In another embodiment, the first insulating layer 506and the first electrode layer 502 can be further patterned to expose aportion of the substrate 500 (e.g. the semiconductor device as shown inFIG. 4 ).

Thereafter, referring to FIG. 5I, electrode contacts 520 a, 520 b and520 c are formed to connecting to the first electrode layer 502, thegate electrode layer 508, and the second electrode layer 518,respectively.

In summary, the semiconductor device according to the inventioncomprises a semiconductor device having a planar stack structurecontaining two source/drain electrodes, a gate electrode layertherebetween, and an oxide semiconductor perpendicularly penetratingthrough the gate electrode layer, and thus the channel length (Lg) canbe defined by the thickness of the gate electrode layer. In other words,according to the invention, fine channel length of the semiconductordevice can be accomplished by simple process.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the disclosed embodimentswithout departing from the scope or spirit of the invention. In view ofthe foregoing, it is intended that the invention covers modificationsand variations provided that they fall within the scope of the followingclaims and their equivalents.

What is claimed is:
 1. A method of manufacturing a semiconductor device,comprising: forming a first electrode layer on a substrate; forming astack structure on the first electrode layer, wherein the stackstructure comprises a first insulating layer, a gate electrode layer,and a second insulating layer; forming an opening in the stackstructure; forming a gate dielectric layer on a sidewall of the openingof the stack structure; forming an oxide semiconductor layer in theopening, wherein the gate dielectric layer is sandwiched between theoxide semiconductor layer and the gate electrode layer; and forming asecond electrode layer on the stack structure to be in direct contactwith the oxide semiconductor layer.
 2. The method of claim 1, whereinafter the step of forming the second electrode layer further comprises:patterning the second insulating layer and the gate electrode layer. 3.The method of claim 1, wherein after the step of forming the secondelectrode layer further comprises: forming a plurality of electrodecontacts connecting to the first electrode layer, the gate electrodelayer, and the second electrode layer respectively.
 4. The method ofclaim 1, wherein the step of forming the gate dielectric layercomprises: conformally depositing a dielectric material layer on thestack structure and in the opening; and etching back the dielectricmaterial layer until the first electrode layer is exposed.
 5. The methodof claim 1, wherein the step of forming the stack structure comprises:depositing the first insulating layer on the first electrode layer;depositing the gate electrode layer on the first insulating layer; anddepositing the second insulating layer on the gate electrode layer. 6.The method of claim 1, wherein the step of forming the oxidesemiconductor layer in the opening comprises: blanket depositing anoxide semiconductor material to fill the opening; and etching back theoxide semiconductor material until the stack structure is exposed. 7.The method of claim 1, wherein a method of forming the oxidesemiconductor layer in the opening comprises a selective depositionprocess.
 8. The method of claim 1, wherein a material of the oxidesemiconductor layer comprises indium-gallium-zinc oxide.
 9. The methodof claim 1, wherein the substrate comprises a silicon-on-insulator (SOI)substrate.